The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device including a buried gate and a method for fabricating the same.
Methods for fabricating a semiconductor device such as a dynamic random access memory (DRAM) are being developed to improve a degree of integration of the semiconductor device. Therefore, attempts have been made to secure reliability and the degree of integration of the semiconductor device by employing a buried gate or a buried word line. The buried gate (or the buried word line) may be implemented by forming a gate buried into a semiconductor substrate and may reduce parasitic capacitance between a word line and a bit line. Further, by employing the buried gate, a sensing margin of the semiconductor device may be improved.
Meanwhile, when using a polysilicon layer in the buried gate technology, a two-layer structure including a low resistance metal layer disposed on the polysilicon layer cannot be used since the horizontal space is limited. Therefore, in the buried gate technology, use of the low resistance layer may be limited to use as a gate electrode over a gate dielectric layer without using the polysilicon layer.
FIG. 1 illustrates a view of a semiconductor device employing a conventional buried gate.
Referring to FIG. 1, the conventional semiconductor device includes a semiconductor substrate 11 where an active region 13 is defined by a device isolation layer 12, a trench 14 formed by simultaneously etching the active region 13 and the device isolation layer 12, a buried gate 16 filling a part of the trench 14 and an inter-layer dielectric layer 17 formed on the buried gate 16 to gap-fill the rest of the trench 14. A gate dielectric layer 15 is formed between the buried gate 16 and the trench 14.
In the prior art illustrated in FIG. 1, the inter-layer dielectric layer 17 gap-fills on the upper side of the buried gate 16 to prevent the buried gate 16 from being oxidized and degraded in a subsequent heating process. The inter-layer dielectric layer 17 uses a silicon oxide layer.
However, the buried gate 16 may be degraded during a subsequent heating process such as an oxidation process. That is, although the buried gate 16 is formed below the inter-layer dielectric layer 17, when performing the oxidation process in an oxidation atmosphere of high temperature, oxygen easily penetrates the inter-layer dielectric layer 17 and the device isolation layer 12 and reaches the buried gate 16, so that the buried gate 16 is oxidized, referring to reference numerals {circle around (1)}, {circle around (2)} and {circle around (3)}. As a result, since the resistance of the buried gate 16 is substantially increased and the reliability of the gate dielectric layer 15 is deteriorated, the reliability of a transistor including the buried gate 16 and the gate dielectric layer 15 is deteriorated.
Further, while not shown, the buried gate 16 may be degraded during various subsequent heating processes as well as the oxidation process.
FIGS. 2A and 2B illustrate images showing problems of prior art methods. That is, FIG. 2A is a defect map and FIG. 2B is a transmission electron microscopy (TEM) image of a defect.
Referring to FIGS. 2A and 2B, in case of forming an oxide layer as the inter-layer dielectric layer 17 on the buried gate 16 having a metal material as the electrode, it is noted that the buried gate may be relatively easily oxidized since the oxygen may penetrate the inter-layer dielectric layer and reach the buried gate in the oxidation atmosphere of the high temperature. That is, an oxide of a metal electrode represented by a reference numeral 19 may be formed.